1. Field of the Invention
The present invention relates to an integrated circuit that allows the user to monitor its internal signals.
2. Description of the Related Art
As information and communication technologies have been tremendously developing these days, it has become increasingly necessary to process a huge amount of information at a very high speed. To achieve this purpose, semiconductor integrated circuits for use in a data storage system or a communications system (e.g., multiple LSIs having the capability of processing analog and digital signals) are often combined together into a single semiconductor chip (which implementation will be referred to herein as a “single-chip LSI”).
If multiple LSIs can be packaged in a single-chip LSI, then the number of electronic components needed to achieve their intended functions can be reduced significantly and the final circuit configuration can be simplified drastically, too. Also, if multiple functions to be usually achieved by a number of components in a single system can be carried out by such a single-chip LSI, then that system can be manufactured at a much lower cost. To further develop today's highly organized information processing networks, it is very important to provide such a system with those sophisticated functions.
However, when multiple LSIs are packaged in a single chip, those functional blocks are interconnected together inside of the single-chip LSI and various signals to be exchanged between those blocks cannot be easily monitored externally, thus making it difficult to evaluate the functional blocks or perform debugging. To overcome those problems, some conventional single-chip LSIs include a monitor terminal for monitoring internal signals.
FIG. 1 is a block diagram showing a configuration for a typical signal processing single-chip LSI. As shown in FIG. 1, the LSI 16 includes a signal processor 10, a register 11, a DRAM 12, a system controller 13, a monitor terminal 14 and an interface 15. The system controller 13 specifies some values determining how the signal processor 10 should operate and stores those settings in the register 11. In accordance with the settings specified in the register 11, the signal processor 10 processes a signal that has been input to this LSI 16 and then transfers resultant signal information to the DRAM 12. Also, the signal processor 10 outputs an internal signal, representing internal information generated while processing the input signal, as a monitor signal to the monitor terminal 14. In response, the monitor terminal 14 outputs the monitor signal, supplied from the signal processor 10, to a circuit outside of the LSI 16. The DRAM 12 stores the processing information that has been received from the signal processor 10. In response to a request that has been externally input through the interface 15, the system controller 13 retrieves the information from the DRAM 12 and outputs it to an outside component by way of the interface 15. Also, in accordance with an instruction that has been externally input through the interface 15, the system controller 13 defines the settings in the register 11. According to the settings specified in the register 11, the types of signals to be output by the signal processor 10 to the monitor terminal 14 may be selected among various internal signals.
FIG. 2 is a block diagram showing a detailed configuration for the signal processor 10 when the LSI 16 is used as a digital read channel for an optical disc drive. As shown in FIG. 2, the signal processor 10 includes an A/D converter 10a, a Viterbi decoder 10b, a demodulator 10c, a PLL 10d and a selector 10e. These functional blocks generate a phase error signal, a frequency error signal, a multi-bit sampling level signal and a digital signal as their respective internal signals.
To do evaluation or debugging on the LSI 16, these internal signals need to be monitored. For that purpose, in the conventional LSI 16, a command to monitor the phase error signal may be externally input to the system controller 13 by way of the interface 15. Then, in accordance with this command, the system controller 13 specifies a value, defining how the selector 10e should operate, in the register 11. According to this setting defined and stored in the register 11, the selector 10e selects the phase error signal from the output signals of the PLL 10d and then outputs it to the monitor terminal 14. If the monitor signal is an 8-bit signal, then the monitor terminal 14 may actually consist of nine terminals including a clock output terminal, for example. In this manner, in the conventional LSI, the settings in the register 11 are defined such that internal information to be monitored outside of the signal processor 10 is output through the monitor terminals 14, and the monitor terminals 14 are subjected to test equipment, for example, thereby checking out the operability of the signal processor 10 and carrying out debugging and evaluation on the processor 10.
However, if those monitor terminals are provided, the number of overall terminals increases, thus raising the cost of the LSI unintentionally. To avoid such an unwanted situation, Japanese Laid-Open Publication No. 2001-228215 discloses a technique of minimizing the number of additional monitor terminals by subjecting a multi-bit monitor signal to parallel-to-serial conversion and then outputting the resultant monitor signal in series.
Nevertheless, even if the monitor signal is output in series, at least one terminal dedicated to monitoring is still required, thus increasing the cost of the LSI to a certain degree.
In addition, to convert the parallel data into serial data, the polarity inversion interval of the monitor terminal needs to be shorter than the situation where parallel data is output through a plurality of monitor terminals. In that case, the current flowing through the monitor terminal will change so frequently as to increase the noise of the LSI noticeably. Such noise may cause some malfunctions in an LSI that should operate at a sufficiently high rate. Accordingly, to allow such an LSI to operate constantly at a desired high rate, it is not preferable to provide those monitor terminals that should increase the noise.
Furthermore, if the monitor signal is output to monitor the internal states of the LSI, then the operation of the LSI might be affected by the noise caused by the monitor signal. That is to say, the operability of the LSI may not be checked out accurately only by the monitor signal.